The present invention relates generally to integrated circuits and methods for memory cells and more particularly to memory cells that offer improved protection against soft errors.
Reduced geometry integrated circuit (“IC”) chip designs are being adopted to increase the density of devices within integrated circuits, thereby increasing performance and decreasing the cost of the ICs. Modem IC memory chips, such as dynamic random access memory (“DRAM”), static random access memory (“SRAM”), and read only memory (“ROM”), are examples of chips having increasingly higher densities and lower costs. Increases in chip density are primarily accomplished by forming smaller structures within devices and by reducing the separation between devices or between the structures that make up the devices. Typically higher density memory chips often operate under lower voltage levels.
Reduced, sub-micron level geometries and reduced operating voltages deployed in these chips make them vulnerable to particle induced soft errors. Typically, soft errors occur when charged particles penetrate a memory cell and cross a junction, creating an abnormal charge that undesirably causes the state of the memory cell to change. Among the common sources of soft errors are alpha particles emitted by contaminants in memory chip packages and/or cosmic rays penetrating the earth's atmosphere. A soft error is typically not caused as a result of any permanent physical defect in the memory cell, and may be fixed by simply writing new data to the invalid memory cell. Occurrences of soft errors typically reduce the reliability of the memory cell.
Functionality and fabrication method of a memory cell such as a conventional SRAM based on complementary metal oxide semiconductor (CMOS) technology is well known. Traditional techniques to reduce the soft error occurrence in the memory cell have focused on increasing the capacitance of the charge storage node(s) of the cell, where charge Q=C*V. The following U.S. patents and technical papers describe various aspects of reducing soft error rates (SER) in memory cells and are incorporated herein by reference:                a) U.S. Pat. No. 6,649,456 entitled ‘SRAM Cell Design For Soft Error Rate Immunity’.        b) U.S. Pat. No. 5,886,375 entitled ‘SRAM Having Improved Soft-Error Immunity’.        c) IEDM-2003 Session-11 “Soft Error Immune 0.46 μm2 SRAM Cell With MIM Node Capacitor By 65 nm CMOS technology For Ultra High Speed SRAM”, Soon-Moon Jung, Samsung, South Korea.        d) “STMicro hardens embedded SRAM against soft errors”, Peter Clarke, Silicon Strategies, Dec. 15, 2003.        
Other conventional SER reduction processes include the Deep_Nwell and polyimide processes. However, many of these conventional techniques often result in increasing the substrate surface area, and/or introducing additional substrate layers. This typically results in fabricating lower capacitor values per unit area of the chip, adds to its complexity and raises its cost.
Thus, a need exists to provide a memory cell that offers improved protection against soft errors. Additionally, it would be desirable for the improved memory cell to offer increased capacitances per unit area, improved SER reliability, be cost effective, and be accommodated in the same substrate area and/or layer structure as a traditional memory cell.